ESLerate


» ESLerate achieves optimal performance through hardware-software trade-offs, while reducing design times from months to hours.

Today’s EDA tool industry consists of a variety of software and design flows.  Many of these tools require the user to purchase or provide their own IP cores for standard library functions, introduce program directive statements to assist the compiler, perform fixed-point quantization, or rewrite the code in order to optimize the hardware design.

ESLerate is the industry’s only high-level synthesis solution that provides a path for translating binary code for general-purpose embedded processors into powerful, tightly-coupled RTL hardware accelerators for SoC FPGA architectures. Whether you are developing in C, C++, Assembly, or a combination thereof, software binaries provide a unified representation for optimizing the performance of your real-time embedded application. ESLerate utilizes these unique characteristics of software binaries to improve performance, area, and power, while minimizing design costs by reducing development and debugging time from months into hours.

ESLerate automatically partitions software binaries into separate hardware and software components. The tool generates the necessary hardware and software communication interfaces and seamlessly reconstructs the software binary with appropriate instructions to communicate with the hardware accelerator. 

ESLerate incorporates advanced techniques and optimizations such as automatic streaming architectures, software and hardware pipelining, and smart scheduling that allow it to generate extremely efficient system-on-chip designs with limited user interaction. It also supports translation of hand coded assembly and legacy code from older processors to new, more efficient FPGA platforms. By allowing hardware-software partitioning at the binary level, more accurate profiling and verification of the complete SoC application may be performed.

ESLerate supports all Xilinx, Altera, and Actel SoC FPGA platforms, and is easily integrated within the industry-standard FPGA development suites. Learn more about support for their SoC FPGA architectures and design flow:

» Key Features and Benefits
  • Implement embedded systems applications on SoC FPGA Platforms
  • Hardware/Software partitioning for compute-intensive applications
  • Hardware synthesis of software binaries and assembly code
  • Automated HW/SW interface synthesis and binary reconstruction
  • Innovative optimizations for highly efficient SoC designs
  • Achieve optimal performance through hardware/software trade-offs
  • Automated testbench generation for bit-true verification
  • Integrated software tool flow with industry-standard design tools
  • Easy-to-use design approach
» Value Proposition
  • Reduce design time of DSP algorithms from months to hours
  • Reduce system cost by migrating from DSPs to SoC Platform FPGAs
  • Migrate legacy assembly code to new, cost-effective FPGA platforms
  • Meet area, performance, cost, and time-to-market constraints

ESLERATE SUPPORTED SOC FPGA ARCHITECTURES

FPGA Manufacturer

Development
Tool

SoC FPGA Platform

Embedded Processor

Bus
Interface

Xilinx

ISE Design Suite

Virtex 2P / 4 / 5 / 6
Spartan 2E / 3E / 6

ARM Cortex-A9
Microblaze
PowerPC 404
PowerPC 440

CoreConnect

Altera

Quartus II

Cyclone II / III
Stratix II / III / IV

Nios II
ARM Cortex-M1

Avalon

Actel

Libero IDE

Fusion
IGLOO
ProASIC3 / 3L

ARM CoreMP7
ARM Cortex-M1
ARM Cortex-M3

AMBA