Electronic System Level Design

» ESL design automation is a proven methodology that reduces the development time and cost of electronic systems by raising the level of abstraction to high-level software models.

Computationally intensive real-time applications, such as 3G and 4G wireless communications and audio/video encoding and decoding, require an integrated hardware-software platform for optimal performance. In these mixed system-on-chip (SoC) platforms, certain portions of the application run in software on a general purpose processor, while others are instantiated as FPGA logic in the form of hardware accelerators. The process for designing such systems is often a difficult one requiring a time-intensive iterative approach for designing and validating the system. Many embedded systems designers, therefore, rely on Electronic Design Automation (EDA) tools to automate this design process.

Electronic System Level (ESL) design uses methodologies and tools that raise the level of design abstraction from the level of logic to that of the algorithm or design behavior. In the ESL design process, high-level synthesis (HLS) tools provide an automated design process that interprets an algorithmic description of a desired behavior and translates it into a hardware model that implements the same behavior. The algorithm is generally modeled in one or more high-level languages such as C, C++, or SystemC. The software model is then analyzed, optimized, architecturally constrained, and scheduled to create a register transfer level (RTL) hardware design. The resulting hardware architecture model in turn is then synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. These higher levels of abstraction also enable system-level analysis, hardware-software partitioning, and easier integration of IP blocks. Thus, very complex, high-performance applications can be designed more quickly, with lower risk and at a lower cost.

ESL design is now an established approach in most of the world’s leading SoC design companies, and is being used increasingly in system design. ESL is continuously evolving into a set of complementary methodologies that enable embedded system design and verification techniques for mixed hardware-software co-designs on SoC FPGA platforms.

Binachip is an ESL design company whose focus is in developing EDA tools that help customers meet the design specifications, radically improved design performance, reduce development costs, and reduce time-to-market constraints.  »Learn More